The present invention relates to a technology for adjusting a delay time of a signal including a clock signal in a semiconductor integrated circuit, and more specifically to the construction of a buffer circuit block and a design method of a semiconductor integrated circuit using the buffer circuit block.
With an increased scale and an increased speed of a semiconductor integrated circuit (called an xe2x80x9cLSIxe2x80x9d hereinafter), a control of a signal delay time in the inside of the LSI, particularly, a decrease of a clock skew in the LSI including a plurality of circuit blocks operating in synchronism with one clock signal, is strongly demanded more and more. In the prior art, various methods have been proposed for decreasing the clock skew.
Referring to FIGS. 1A and 1B, FIGS. 2A and 2B, and FIG. 3, different prior art methods for decreasing the clock skew are illustrated.
FIG. 1A is a flow chart for illustrating the process disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-10-011494 (called a xe2x80x9cfirst prior artxe2x80x9d hereinafter), and FIG. 1B is a circuit diagram showing the example shown in Japanese Patent Application Pre-examination Publication No. JP-A-10-011494. In FIG. 1B, the reference number 922 indicates a clock generating circuit, and the reference numbers 923, 924, 925, 926, 927, 928 and 929 designate a buffer. The reference numbers 930, 931, 932 and 933 show a flipflop. In FIG. 1B, only a clock line is shown, so that a signal line is not shown. In a process shown in the flow chart of FIG. 1A, in the first prior art, buffers on a clock line in a clock tree are replaced with buffers having a different input logic threshold, so that the delay amount of the buffer is changed by utilizing an output waveform dulling of a preceding stage, whereby the clock skew is decreased.
FIGS. 2A and 2B show circuit diagrams illustrating clock trees formed in accordance with the method disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-08-274260 (called a xe2x80x9csecond prior artxe2x80x9d hereinafter). In FIGS. 2A and 2B, the reference numbers 1011 to 1048 designate drivers having a largest drive capability, and the reference numbers 1022a to 1048a indicate drivers having a small drive capability. The reference numbers 1051 to 1058 show a flipflop In addition, only a clock line is shown, so that a signal line is not shown. In the circuitry shown in FIG. 2A composed of largest drive capability drivers located in accordance with a clock tree method, paths excluding a path having a maximum signal delay value from a second stage in the clock tree to a block circuit (flipflop) are modified by replacing one or more largest drive capability drivers with a previously prepared driver having a small driving capability so that the a signal delay time of each path becomes equal to the maximum signal delay value, whereby a clock skew is decreased.
FIG. 3 is a flow chart illustrating a method disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-10-335470 (called a xe2x80x9cthird prior artxe2x80x9d hereinafter). In this third prior art, a placement and routing are carried out for cells in a sequential circuit operating in synchronism with a clock signal, cells in a combinational circuit operating to receive an output of the sequential circuit, and clock buffer cells for supplying the clock signal to the sequential circuit (Step S1). A driving load of the clock buffers in a clock supplying system obtained in the placement and routing is analyzed (Step S2), and a driving capability of the clock drivers are set in accordance with the driving load of the clock buffers (Steps S3 and S4), whereby the skew of the clock signal is highly precisely controlled.
The above mentioned methods of the prior art can be said that a buffer in the clock tree is replaced with another, the input logic threshold or the driving capability of the buffer is changed for adjustment of the delay. Accordingly, if it is sufficient if the clock skew is decreased to a certain limited degree, a deserved advantage can be obtained. However, the replacement of the buffer gives influence the characteristics of the clock tree and a peripheral circuit thereof, or alternatively, an input capacitance of the buffer itself changes. Therefore, unless a delay simulation of an actual routing is executed after the buffer replacement, it is not possible to know to what extent the skew is finally decreased. Accordingly, there is a limit in decreasing the skew.
Furthermore, in a specific signal path having a designated highly precise signal delay amount, when the signal delay of the specific signal path exceeds an admissible limit, it becomes necessary to change the placement and routing in blocks on the path.
Accordingly, it is an object of the present invention to overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a buffer circuit block capable of easily and highly precisely controlling the delay of a clock signal or a transmitted signal in a clock supplying system or a signal transmission system of the LSI.
Still another object of the present invention is to provide an LSI design method utilizing the buffer circuit block in accordance with the present invention.
The above and other objects of the present invention are achieved in accordance with the present invention by a buffer circuit block for use in a semiconductor integrated circuit, including an input part, an delay adjusting part and an output part, a delay amount of the delay adjusting part being able to be changed within a predetermined range while fixing at least an input terminal capacitance of the input part having an input terminal and a driving capability of the output part including a load dependency.
According to another aspect of the present invention, there is provided a buffer circuit block for use in a semiconductor integrated circuit, including an input part, an delay adjusting part and an output part, each including a plurality of transistors, a delay amount of the delay adjusting part being able to be changed within a predetermined range while fixing at least the position of an input terminal provided in the input part, the position of an output terminal provided in the output part, an external shape and an external size of the buffer circuit block, the shape and the size of the transistors included in the input part, and the shape and the size of the transistors included in the output part.
In the above mentioned buffer circuit block, the delay amount of the delay adjusting part can be changed within the predetermined range while fixing a placement and routing inhibition region where placement and routing of an element that is not included in the buffer circuit block is inhibited within an area of the buffer circuit block.
Furthermore, the plurality of transistors included in the delay adjusting part can include a plurality of transistors having the same conductivity type but having different sizes.
In addition, the input part can include at least one unitary cell constituted of a p-channel field effect transistor and an n-channel field effect transistor, and the delay adjusting part can include a plurality of unitary cells each constituted of a p-channel field effect transistor and an n-channel field effect transistor.
Furthermore, the output part can include a plurality of parallel-connected unitary cells each constituted of a p-channel field effect transistor and an n-channel field effect transistor.
According to still another aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit which includes at least a clock signal driving circuit block, and a plurality of first circuit blocks operating in synchronism with a clock signal supplied from the clock signal driving circuit block, the method including:
a library preparation step to previously prepare at least one delay adjusting block group including a plurality of buffer circuit blocks each of which includes an input part, an delay adjusting part and an output part, and which are the same in connection with an input terminal capacitance of the input part, a driving capability of the output part including a load dependency, and an internal logical operation but have different signal delay values of the delay adjusting part, and then, to register the delay adjusting block group into a circuit library;
a first circuit design step to select, when a circuit design of the semiconductor integrated circuit is carried out by using the circuit library, a first buffer circuit block having a predetermined signal delay value from the circuit library and to insert the selected first buffer circuit block into each clock path of a clock net for interconnecting at least the clock signal driving circuit block and the plurality of first circuit blocks, so as to generate a first circuit connection information of the semiconductor integrated circuit;
a first layout step to execute placement and routing on the basis of the circuit library and the first circuit connection information to generate a first layout information;
an actual routing delay simulation step to execute the actual routing delay simulation of the semiconductor integrated circuit by using a predetermined information including parameters extracted from the first layout information;
a delay information extraction step to extract a signal delay value information of each of various paths of the LSI including the clock net, from the result of simulation obtained in the actual routing delay simulation step;
a first skew confirmation step to compare the signal delay value of each clock path extracted in the delay information extraction step, with a predetermined standardized value and to compare the skew of the clock net with a first predetermined standardized value so as to discriminate whether or not a timing error exists;
when at least the skew of the clock net is larger than the first predetermined standardized value, a first skew adjustment step to modify the placement and routing of the circuit blocks included in the clock net and replace the circuit blocks included in the clock net excluding the first buffer circuit block with another, so as to generate a second circuit connection information and a second layout information;
until at least the skew of the clock net becomes not greater than the first standardized value, the first skew adjustment step, the actual routing delay simulation step, the delay information extraction step and the first skew confirmation step are repeated;
when the skew of the clock net becomes not greater than the first standardized value, a second skew confirmation step to compare the signal delay value of each of the clock paths included in the clock net extracted from the result of the actual routing delay simulation, with the signal delay value of a predetermined first clock path, to extract all second clock paths each having the signal delay value different from the signal delay value of the predetermined first clock path by a value larger than a second standardized value; and
a second skew adjustment step to select, for each of all the second clock paths, from the delay adjusting block group, a second buffer circuit block having a delay value sufficient to make the difference between the signal delay value of the second clock path concerned and the signal delay value of the predetermined first clock path, not larger than the second standardized value, to replace the first buffer circuit block in the second clock path concerned with the selected second buffer circuit block so as to generate a third layout information.
According to a further aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit which includes a digital circuit required to have a first signal path having a signal delay time within a predetermined error range from a predetermined desired signal delay time, the method including:
a library preparation step to previously prepare at least one delay adjusting block group including a plurality of buffer circuit blocks each of which includes an input part, an delay adjusting part and an output part, and which are the same in connection with an input terminal capacitance of the input part, a driving capability of the output part including a load dependency, and an internal logical operation but have different signal delay values of the delay adjusting part, and then, to register the delay adjusting block group into a circuit library;
a first circuit design step to select, when a circuit design of the semiconductor integrated circuit is carried out by using the circuit library, a first buffer circuit block having a predetermined signal delay value from the circuit library to insert the selected first buffer circuit block into the first signal path so as to generate a first circuit connection information of the semiconductor integrated circuit;
a first layout step to execute placement and routing on the basis of the circuit library and the first circuit connection information to generate a first layout information;
an actual routing delay simulation step to execute the actual routing delay simulation of the semiconductor integrated circuit by using a predetermined information including parameters extracted from the first layout information;
a delay information extraction step for extracting a signal delay value information of each of various paths of the semiconductor integrated circuit including the first signal path, from the result of simulation obtained in the actual routing delay simulation;
a first delay confirmation step to compare the signal delay value of each path extracted in the delay information extraction step, with a predetermined standardized value, and to compare an absolute value of a difference between the signal delay path of the first signal path and the desired signal delay value, with a predetermined first standardized value so as to discriminate whether or not a timing error exists;
when the absolute value of the difference between the signal delay path of the first signal path and the desired signal delay value is larger than the a predetermined first standardized value, a first delay adjustment step to modify the placement and routing of the circuit blocks included in the first signal path or to replace the circuit blocks excluding the first buffer circuit block by another, so as to generate a second circuit connection information and a second layout information;
until the absolute value of the difference between the signal delay path of the first signal path and the desired signal delay value becomes not larger than the first standardized value, the first delay adjustment step, the actual routing delay simulation step, the delay information extraction step and the first delay confirmation step S61 are repeated;
when the absolute value of the difference between the signal delay path of the first signal path and the desired signal delay value becomes not larger than the first standardized value, a second delay confirmation step to discriminate whether or not the absolute value of the difference between the signal delay path of the first signal path and the desired signal delay value becomes not larger than a second standardized value; and
when the absolute value of the difference between the signal delay path of the first signal path and the desired signal delay value becomes not larger than the second standardized value, a second delay adjustment step to select, from the delay adjusting block group including the first buffer circuit block on the first signal path, a second buffer circuit block having a delay value sufficient to make the absolute value of the difference between the signal delay value of the first signal path concerned and the desired signal delay value, not larger than the second standardized value, to replace the first buffer circuit block in the first signal path concerned with the selected second buffer circuit block so as to generate a third layout information.
In the above mentioned method, the plurality of buffer circuit blocks included in the delay adjusting block group can be the same in connection with a routing inhibition region within each buffer circuit block.
Furthermore, the circuit library can include a plurality of delay adjusting block groups, and a maximum signal delay value of the plurality of buffer circuit blocks included in the same delay adjusting block groups is different from one to another of the plurality of delay adjusting block groups.
Assuming that the maximum signal delay value and a minimum signal delay value of the plurality of buffer circuit blocks included in the same delay adjusting block groups are xe2x80x9ctpdmaxxe2x80x9d and xe2x80x9ctpdminxe2x80x9d, respectively, the circuit library can include at least one delay adjusting block groups having a difference of {tpdmaxxe2x88x92tpdmin} larger than the first standardized value.